module Freq_div #(
    parameter base_CLK = 50_000_000
) (
    input      clk,
	 input [24:0]N,//分频数
    output reg out
);
  reg [24:0] count = 0;
  always @(posedge clk) begin
    count <= count + 1;
    if (count == N) begin
      count <= 0;
      out   <= ~out;
    end
  end
endmodule
